Modeling Ballistic Carbon Nanotube FETs
Modeling of CNFET devices is usually done numerically to ascertain the current-voltage characteristics. This requires a self consistent solution of Schrödinger's equation and Poisson's equation along with the transport equations in the channel. A self consistent solution requires numerical iterations and ultimately convergence to a solution. However, for a compact model that can be used in a circuit solver like SPICE, such a model is impractical for the simulation of a circuit consisting of multi-transistors. Herein lies the importance of a compact model for CNFETs. We have developed a simplified circuit compatible model for ballistic single-walled CNFETs, which removes the self consistency and makes a many-transistor circuit "simulate-able". We have used appropriate approximations and fitting functions. A typical numerical device model determines the drain current and gate voltage relation (ID - VG) of a ballistic CNFET. It involves a self consistent solution of Poisson's and Schrödinger's equations to find the amount of charge in the channel. We have linearized the flow so that for a given set of terminal voltages (VD, VG and VS) we can determine ID and the capacitances CGS and CGD. Simulation results demonstrate that this flow can be easily implemented in an SPICE-like circuit simulator and CNFET circuits can be easily simulated for power and performance. Fig. 5a shows the schematic diagram of the compact model. We have developed equations describing IDS, CGS and CGD as functions of the terminal voltages, namely, VD, VS, and VG. Analysis shows a good match between numerical device simulations and the compact model. We have simulated adders, multipliers and other digital logic blocks with our developed model. The power performance trade-offs in CNFET based digital logic design can now be well estimated and understood.
(a) The schematic of the CNFET model.
(b) Simulation of an adder illustrating the rippling of the carry signal.
(c)A power performance trade-off of CNFETs (with intrinsic load and 2fF load) vis-a-vis Silicon MOSFETs for the adder at several VDD voltages (400mV to 800mV at steps of 100mV)